module ram2PortDataoutCrossBar (
    input wire clk,
    input wire rst,
    input wire [15:0] data_en_in,
    input wire [31:0] data_in [0:15],
    input wire [15:0] set_en,
    input wire [5:0] set_from [0:15],
    output reg [15:0] data_en_out,
    output reg [31:0] data_out [0:15]
);
    integer i;
    reg [5:0] history_channal_from [0:15];
    reg [1:0] work_state [0:15];

    always @(posedge clk) begin
        if (rst) begin
            data_en_out <= 0;
            for (i=0; i<16; i=i+1) begin
                data_out[i] <= 0;
                history_channal_from[i] <= 16;
                work_state[i] <= 2'b00;
            end
        end
        else begin
            for (i=0; i<16; i=i+1) begin
                if (work_state[i]==2'b00 && set_en[i]) begin
                    history_channal_from[i] <= set_from[i];
                    work_state[i] <= 2'b01;
                end

                if (work_state[i]==2'b01) begin
                    if (data_en_in[history_channal_from[i]]) begin
                        data_en_out[i] <= 1;
                        data_out[i] <= data_in[history_channal_from[i]];
                        work_state[i] <= 2'b10;
                    end
                end

                if (work_state[i]==2'b10) begin
                    if (data_en_in[history_channal_from[i]]) begin
                        data_en_out[i] <= 1;
                        data_out[i] <= data_in[history_channal_from[i]];
                    end
                    else begin
                        //传输完成后，关闭通道
                        history_channal_from[i] <= 16;
                        data_en_out[i] <= 0;
                        data_out[i] <= 0;
                        work_state[i] <= 2'b00;
                    end
                end
            end
        end
    end
endmodule